Electrical Engineering

Non-Capstone Projects

In addition to the Electrical and Computer Engineering capstone projects, an additional Electrical and Computer Engineering class displays their work at Design Day:

ECE 101 is an elective course introducing freshmen students to Electrical and Computer Engineering through a series of innovative hands-on laboratory experiments linked to new research and teaching areas. These experiments include (a) maple-seed robotic fliers (MRF) with onboard electronics, (b) brainwaves-I; mind-controlled games and robots using EEG sensors, (c) C programming of robots based on MSP430 microcontrollers and NXT LEGO controllers, (d) computer switches, (e) pH measurement using NXT sensors, (f ) nanotechnology study using a LEGO gear-train, (g) brainwaves-II; mind-controlled games using MATLAB programming, (h) renewable energy resources using windmill and solar cells, (i) location of bio-molecules using RFID.

ECE 101 Photo

ECE 101 projects will be exhibited on the second floor of the Engineering Building in the 2200 Hallway from 9:00 until noon.

Please see the Design Day Booklet for more information.


Students in ECE 410 will be challenged to design the schematic and physical layout of a programmable FIR filter. FIR (Finite Impulse Response) filters are one of two main types of digital filters used in Digital Signal Processing (DSP) applications (the other type being IIR). In this semester, an FIR filter will be designed and constructed in terms of power, area and also delay. The elementary structures of an FIR filter are a combination of multipliers and delays, which represent the combination of adders. However, adders serve as the basic components in the implementation of an FIR filter. Moreover, it is one of the fundamental arithmetic operations used extensively in many VLSI systems such as microprocessors and application specific DSP architectures. It participates in many other useful operations such as subtraction, multiplication, division etc. Thus, a programmable FIR Filter will be implemented, including “programming” (e.g. download/upload) memory tapes using CMOS circuitry and Cadence VLSI design tools.

Their Results will be judged on their ability to satisfy several competing goals:

  1. Minimization of the total area
  2. Power
  3. Speed

ECE 410 projects will be exhibited on the second floor of the Engineering Building in the 2200 Hallway from 9:00 until noon.

Please see the Design Day Booklet for more information.